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SharkyForums.Com - Print: What is DDR exactly?

What is DDR exactly?
By Chrogg April 30, 2001, 08:30 PM

I know it stands for Double Data Rate, but how how the DDR architecture different, if at all?

I mean, what is the difference between, say, 100Mhz DDR (effectively 200MHz) and just normal 200MHz? Is it just that with DDR, data is processed on the peak and trough of each CPU cycle, and with normal 200MHz data is only processed once per cycle, but there are twice as many cycles per second?

By Moridin May 01, 2001, 11:19 AM

Basically what happens with DDR is that you transfer data on both the rising and falling edge of the processor clock. Normal (SDR) transfers only occur on either the rising or falling edge of the clock.

For example say you have a memory system that has a clock, 64 data lines, and 32 address lines. (In reality you would have some other control signals as well). Real DRAM works somewhat differently, so this is not an explanation of how a DRAM bus works this explanation is to illustrate the general idea behind DDR.

When the chipset wants to get data from memory it puts the address of the data it wants on the address lines. Then it activates one of those other control lines to tell the memory that it should do something. The memory responds waiting several clock cycles (to retrieve the data) then it puts the values in that memory location on the data lines on the next falling edge of the clock.

It doesn't end there though, because we are talking about synchronous memory it doesn't just return 1 value. It returns an entire cacheline which can be 32 Bytes (4 transfers) for a PIII, or 64 Bytes (8 transfers) for an Athlon.

In regular SDRAM each of these transfers would take place on a the next falling edge of the clock. DDR however doesn't wait for the next falling edge it puts the data there on the next (rising) edge.

In effect, as far as the data lines are concerned the clock is actually running twice as fast.

The reason this is better then actually running the clock twice as fast is that the frequency of the clock is normally twice as high as the frequency on the data and address lines. In SDR the data lines can change from low to high in one clock cycle and then back to low in the next. Therefore it takes two complete clock cycles to make one complete cycle on the data lines.

This means that your clock signal don't need to run faster then the rest of the system and no longer artificially limit your data speed.

I hope this gives you at least an idea of how and why DDR works. Remember this is not a description of a real memory bus just a made up example to show how DDR works. This is so I can avoid confusing you with details of a real implementation. (It also means I don't need to do any research to make sure I didn't screw up on the details of the implementation. ) This is a valid way to explain this since the same principles are used in many different DDR implementations.

By Chrogg May 02, 2001, 04:33 AM

Thanks for the information .

By UT Dominator May 02, 2001, 06:59 AM

and just in case you were wondering about rambus RDRAM, it's quad pumped. That is it can transfer data on the rising and falling edges as well as the leading and trailing edges. all four intersections of the underscores and slashes below

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By Moridin May 02, 2001, 09:45 AM

quote:Originally posted by UT Dominator:
and just in case you were wondering about rambus RDRAM, it's quad pumped. That is it can transfer data on the rising and falling edges as well as the leading and trailing edges. all four intersections of the underscores and slashes below

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Actually current RDRAM is double pumped. There is a standard for quad data rate RDRAM, but it is currently limited to a channel length of 4 inches. This makes it suitable for things like communications equipment and graphics, but not main memory in a PC.

Quad rate Rambus doesn't make transfers any faster then DDR, but every transfer moves two bits instead of one on each data line. This is accomplished by using 4 signal levels instead of two. (I.E. 0V=00 1V=01 2V=10 3V=11.) This is similar to the distinction between baud rate and bit rate for a modem.

The Quad pumped FSB of the P4 works a little differently. I am not really up on the details, but if I understand correctly it uses two clocks phase shifted by 90 deg.

By bobgod007 May 03, 2001, 02:08 AM

quote:Originally posted by Moridin:
Actually current RDRAM is double pumped. There is a standard for quad data rate RDRAM, but it is currently limited to a channel length of 4 inches. This makes it suitable for things like communications equipment and graphics, but not main memory in a PC.

Quad rate Rambus doesn't make transfers any faster then DDR, but every transfer moves two bits instead of one on each data line. This is accomplished by using 4 signal levels instead of two. (I.E. 0V=00 1V=01 2V=10 3V=11.) This is similar to the distinction between baud rate and bit rate for a modem.

The Quad pumped FSB of the P4 works a little differently. I am not really up on the details, but if I understand correctly it uses two clocks phase shifted by 90 deg.


I believe its called strobing. Also, if I understand correctly, the actual capacitors in the RAM (assuming its dynamic or DRAM) don't necceirally switch on both edges of the clock. The actual bus interface and internal workings don't thus exactly sync. This is why DDR RAM does not have twice the bandwidth of SDR RAM (and why 2x and 4x AGP aren't twice and four times as efficient as 1x AGP in terms of overall performance).


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