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  • SharkyForums.Com - Print: Mckinley

    Mckinley
    By Xcom_Cheetah June 14, 2001, 11:03 PM

    i just read that Mckinley processor have 7 stage pipeline (30% shorter than Itanium) and 1.2 Ghx frequency... (around 50% higher than Itanium) how can that be..?? i mean isn;t the next processor is supposed to have larger pipeline to have higher clock speed... ?? like P4 over PIII.. can anybody shed light on it..

    By Moridin June 15, 2001, 09:44 AM

    quote:Originally posted by Xcom_Cheetah:
    i just read that Mckinley processor have 7 stage pipeline (30% shorter than Itanium) and 1.2 Ghx frequency... (around 50% higher than Itanium) how can that be..?? i mean isn;t the next processor is supposed to have larger pipeline to have higher clock speed... ?? like P4 over PIII.. can anybody shed light on it..

    Better work on the part of the engineers involved most likely, though to be fair they had the benefit of being able to learn from the problems in Itanium.

    To me the surprise has always been that Itanium runs as slowly as it does. With a 10-stage pipeline, new instruction set, and no scheduling to worry about I thought it should have reached much higher speeds then 800 MHz in .18 Al.

    By Arcadian June 15, 2001, 10:59 AM

    quote:Originally posted by Moridin:
    Better work on the part of the engineers involved most likely, though to be fair they had the benefit of being able to learn from the problems in Itanium.

    To me the surprise has always been that Itanium runs as slowly as it does. With a 10-stage pipeline, new instruction set, and no scheduling to worry about I thought it should have reached much higher speeds then 800 MHz in .18 Al.

    The current Itanium, also called Merced, had been a work in progress for almost as long as the P6. However, it was put through several process generations without the benefit of a redesign such as the P6 had received through process generations, so it really wasn't taking full advantage of the 180nm process. McKinley was designed from the beginning for 180nm, and like you said, it learns from a lot of the mistakes of Merced, thus allowing for a more elegant ground up design, as opposed to patches and fixes to make an old design work with new technology.

    By Moridin June 15, 2001, 11:12 AM

    quote:Originally posted by Arcadian:
    The current Itanium, also called Merced, had been a work in progress for almost as long as the P6. However, it was put through several process generations without the benefit of a redesign such as the P6 had received through process generations, so it really wasn't taking full advantage of the 180nm process. McKinley was designed from the beginning for 180nm, and like you said, it learns from a lot of the mistakes of Merced, thus allowing for a more elegant ground up design, as opposed to patches and fixes to make an old design work with new technology.

    Good point the long design cycle of Merced is probably a factor as well, though I still think learning for the mistakes made in Merced is the biggest factor. The Merced design team undoubtedly went down many paths that proved to be dead ends and painted themselves into corners many time just because they were working in uncharted waters.

    By gammaray51 June 15, 2001, 12:01 PM

    With all of the branch perdiction and predicates that they built into the instruction architecture I thought they would try and extend the pipeline further.

    By idris5 June 15, 2001, 12:10 PM

    I wonder, being as Itanium is such a big chip, what the critical signal paths are like?

    Perhaps the clock rate was constrained because the layout of the chip was such that propagation time of signals between functional units was a problem.

    I would also be interested to find out what the respective cache latencies are?

    By James June 15, 2001, 12:18 PM

    quote:Originally posted by idris5:
    Perhaps the clock rate was constrained because the layout of the chip was such that propagation time of signals between functional units was a problem.

    I could have sworn I remember reading something about a "distributed clock", basically several clock generators, that was being implemented to overcome that problem?

    As always, somebody please correct me if I am wrong.

    By Moridin June 15, 2001, 12:56 PM

    quote:Originally posted by idris5:
    I wonder, being as Itanium is such a big chip, what the critical signal paths are like?

    Perhaps the clock rate was constrained because the layout of the chip was such that propagation time of signals between functional units was a problem.

    I would also be interested to find out what the respective cache latencies are?

    I think that may be a good guess. IIRC McKinley is also about half the size of Itanium.

    By Xcom_Cheetah June 15, 2001, 10:27 PM

    i haven't heard anything like this b4... i mean PIII has 10 stage and it hardly reached 1.4 GHz. and thats even on .13 micron process... Athlon have 12 stage.. i think G4 or G5 have 7 stage pipeline and even then it starts from something like 500MHz and i m not sure will it reach 1.2GHz.. so i just want to know if there is something special they implemented in Mckinley like trace cache to put some stages out of critical pipeline...

    and secondly y r they not refining and fine-tuning Itanium... ??

    By gammaray51 June 18, 2001, 01:07 PM

    quote:Originally posted by Xcom_Cheetah:

    and secondly y r they not refining and fine-tuning Itanium... ??

    What exactly do you mean by this? From what I can tell intel is doing what they can to correct the problems that have arised in itanium.

    By Arcadian June 18, 2001, 01:10 PM

    quote:Originally posted by Xcom_Cheetah:
    Athlon have 12 stage..

    and secondly y r they not refining and fine-tuning Itanium... ??

    1) Athlon has 10-11 stages, depending on the instruction. The floating point pipeline is 15 stages.

    2) McKinley is Intel's way of improving Itanium performance.

    By idris5 June 18, 2001, 02:30 PM

    quote:I could have sworn I remember reading something about a "distributed clock", basically several clock generators, that was being implemented to overcome that problem?

    This technique reduces the problem of clock skew, but signals will still take a period of time to propogate between functional units and the bigger the chip the longer the route is - hence this can reduce the maximum clock rate as you have to wait for signals to arrive (or lose a clock cycle such as the drive stages in the P4 pipeline).

    Clock skew, BTW, is a problem whereby the clock is generated in the centre(ish) of the chip and the signal propagates outwards from here to the functional units. At high clock rates, depending on the path of the clock tree, the clock signal can arrive at one functional unit before another. If the units are adjacent to one another then you could get one unit trying to change the signal on a bus just as the other is trying to read it - causing another problem known as metastability.

    Various methods of producing clocks and types of clock tree can be used to overcome this problem, and one of these methods is to create lots of clocks locally for the units and have cental buses on a master clock to synchronise and buffer everything.

    By pm June 18, 2001, 10:50 PM

    quote:Originally posted by idris5:
    At high clock rates, depending on the path of the clock tree, the clock signal can arrive at one functional unit before another. If the units are adjacent to one another then you could get one unit trying to change the signal on a bus just as the other is trying to read it - causing another problem known as metastability.
    This is an excellent explanation, but I have one minor point. Rather than metastability, I refer to this as a "race" (referring to the fact that the logic, or bus in this case, beat the clock in the race to the latch), or, more formally, as a hold time violation.

    My fingers have been itching to join this conversation since you are talking about a chip that I have spent a lot of time and effort working with a team to turn into reality, but, of course, I can't. NDA's suck.

    By Moridin June 18, 2001, 11:34 PM

    quote:Originally posted by pm:
    [QUOTE]Originally posted by idris5:
    [b]

    My fingers have been itching to join this conversation since you are talking about a chip that I have spent a lot of time and effort working with a team to turn into reality, but, of course, I can't. NDA's suck.

    Hehe. Relax. I'm sure we will all find out the truth eventually. Despite our desire to know now the last thing any of us want is for you to jeopardize your career just to satisfy our curiosity. So whatever you do don't violate that NDA

    By Xcom_Cheetah June 18, 2001, 11:54 PM

    isn;t Mckinley is a new design... i don;t think its the extension of Itanium... or is it.??

    By idris5 June 19, 2001, 10:52 AM

    mmm NDA's, necessary and important as they are, can be annoying at times.


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