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  • SharkyForums.Com - Print: Any Info About Intel`s new Chipset??

    Any Info About Intel`s new Chipset??
    By Diablo SV July 08, 2001, 07:29 PM

    Hi
    I like to have any info anybody says about the Upcomeing intel `Tulloch' Chipset...
    Thanx

    By Marsolin July 09, 2001, 11:57 AM

    It's supposed to add 4i RDRAM support. 4i stands for 4 independent bank technology which lowers the production cost. The speed will probably be similar to current RIMMs.

    By Moridin July 09, 2001, 12:18 PM

    quote:Originally posted by Marsolin:
    It's supposed to add 4i RDRAM support. 4i stands for 4 independent bank technology which lowers the production cost. The speed will probably be similar to current RIMMs.

    Shouldn't this educe the number of open banks and reduce the chance of a page hit. (thus reducing performance?) Or is this not really an issue since the chipsets are not using this capability anyway?

    By Marsolin July 09, 2001, 12:33 PM

    quote:Originally posted by Moridin:
    Shouldn't this educe the number of open banks and reduce the chance of a page hit. (thus reducing performance?) Or is this not really an issue since the chipsets are not using this capability anyway?

    I've heard speculation on that as well, but most people I've talked to think the performance hit will be minimal on average. Maybe up to couple percent at times. Of course we won't know for sure until Tulloch samples are available, which is still some time in the future.

    By Arcadian July 09, 2001, 05:38 PM

    quote:Originally posted by Moridin:
    Shouldn't this educe the number of open banks and reduce the chance of a page hit. (thus reducing performance?) Or is this not really an issue since the chipsets are not using this capability anyway?

    Actually, performance may even be increased with only 4 banks. The reason is because current 16 bank RIMMs have high latency troubles bank switching every time a new address is requested that is not in the currently open bank. Because of power concerns and chipset electricals, only a few banks may be open at one time. Having a 4 bank design may be the sweet spot in performance between having too many and too few banks.

    Besides, there is also rumor that Tulloch may support PC1066 RDRAM, which will also have the benefit of much better bandwidth, increasing overall performance.

    By Diablo SV July 10, 2001, 08:57 AM

    What about Other Things Like will it have the ICH3, PCI-X or IEEE 1394?
    And What about the PC1200 RDRAMS? they should by as same as the PC1066 right?

    By Marsolin July 10, 2001, 11:02 AM

    quote:Originally posted by Diablo SV:
    What about Other Things Like will it have the ICH3, PCI-X or IEEE 1394?
    And What about the PC1200 RDRAMS? they should by as same as the PC1066 right?

    ICH3 is skipping the desktop, so Tulloch should have ICH4 which will add USB2.0. I don't expect to see PCI-X or 1394 integrated at that time. PCI-X will probably only be available in workstation chipsets. I would also be surprised to see PC1066 officially supported right away, although it would be sweet.

    Tulloch is also supposed to allow single or dual channel RDRAM that is automatically set based upon what RIMM configs are installed. That's only a benefit for someone looking for a low price rather than performance system though.

    By Diablo SV July 10, 2001, 09:57 PM

    Thanx Guy`s

    By leoku July 11, 2001, 02:56 PM

    quote:Originally posted by Arcadian:
    Actually, performance may even be increased with only 4 banks. The reason is because current 16 bank RIMMs have high latency troubles bank switching every time a new address is requested that is not in the currently open bank. Because of power concerns and chipset electricals, only a few banks may be open at one time. Having a 4 bank design may be the sweet spot in performance between having too many and too few banks.

    Besides, there is also rumor that Tulloch may support PC1066 RDRAM, which will also have the benefit of much better bandwidth, increasing overall performance.

    This could be similar to either crossbar memory controller found on mainframes or memory interleaving.

    Expect performance boost greatly. As far as efficiency, it still depends on which one Intel will use, crossbar memory architecture is currently proven in mainframes and supposedly faster then interleaving architecture since the latter uses shared bandwidth.

    By Moridin July 11, 2001, 03:42 PM

    quote:Originally posted by leoku:
    This could be similar to either crossbar memory controller found on mainframes or memory interleaving.

    Expect performance boost greatly. As far as efficiency, it still depends on which one Intel will use, crossbar memory architecture is currently proven in mainframes and supposedly faster then interleaving architecture since the latter uses shared bandwidth.


    This refers more to the internal structure of the DRAM. (Though of course the memory controller still must support it) SDRAM and DDR SDRAM have always used 4 banks per DIMM. Some chipsets like the BX could keep 4 banks open per DIMM.

    RDRAM used 16 or 32 banks per chip and operates serially. This means that a channel with 16 chips on it could have as many as 512 bank open of which 256 could be open simultaneously. I don't know about the i850, but the i820 could only have 8 open at one time while the i840 was either 8 or 16 (I don't recall which).

    If I am not mistaken the banks in the new modules o not share sense amp circuitry and therefor are not restricted to half the total number of banks being open. This would mean that if you had 8 chips in a channel you could still have 32 open banks (16 chips X 4 would be 64) this is less then before, but you would not have to worry about bank contention like you did in previous RDRAM modules.

    I guess this answers my performance question. The number of banks is still quite high, probably better then the number the chipset actually keeps open so it doesn't hurt performance and the independent nature of the banks is likely to increase performance.

    Does this seem right to people? Have I missed something or just made outright errors?

    By Diablo SV July 11, 2001, 04:17 PM

    And I read latly a lot about that Rambus Yellow Stone thing which said that it should have about 6.4GB\s of bandwidth abd should be used in the Tulloch, well any more info about this??

    By Arcadian July 11, 2001, 07:25 PM

    quote:Originally posted by Moridin:
    I guess this answers my performance question. The number of banks is still quite high, probably better then the number the chipset actually keeps open so it doesn't hurt performance and the independent nature of the banks is likely to increase performance.

    Does this seem right to people? Have I missed something or just made outright errors?

    I agree. That's how I see it.


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