|
|
SE: There are several companies shipping graphics chips intended for Laptops with embedded DRAM, yet they are all poor performers when compares to desktop solutions with off-chip DRAM. What makes the Glaze3D technology different?
SL: The principle difference is in approach. The laptop guys have been using embedded memory for the benefits of power, real estate and overall solution costs. They have not been able to exploit the true benefits of bandwidth and speed due to the fact that it is almost completely counter to their main objectives.
XBA is designed around performance enhancement first and foremost. We have a very wide data path, 512 bit, which is 4 times that of products that have been announced by nVidia or 3dfx. We do not have the severe limits on power budget as the notebook market and we also have more room in terms of die size and cost of our solution. The market is quite different for enthusiast gamers and mainstream or even performance notebook buyers. XBA is built for speed, pure and simple.
SE: According to the web site, the Glaze3D chip will be built on a .20 micron 130mm^2 die with 9MB of embedded DRAM, all running at 150MHz. This appears to be a difficult chip to make. Is this the case?
SL: Any chip of this size built in an advanced, deep-submicron technology is a difficult chip to make. In our case this is further complicated by the embedded DRAM, but by working together with Infineon, we have been able to complete this pioneering project.
SE: What problems have you run into with the development of the Glaze3D chip?
SL: The architecture is so different we had a great deal of new challenges, which really the industry had never been forced to address. We can't forget e talking about a processor that is an 8-texel pipeline with 9 MB of very high-speed memory on one monolithic die, the part is very complex. I do absolutely know that we did underestimate some of the tasks in getting a part this large through the final stages of the process. We have addressed these in full and learned a great deal about what we believe the future to be; high speed embedded memory and logic control.
SE: The Glaze3D design includes four separate 128-bit pathways running from the MMU to four 18Mbit memory modules, or a 512-bit wide bus. The interface between the MMU and the framebuffer stage is split into two 128-bit read paths and two 128-bit write paths. While the whole bus added together comes to 512-bit, it is not 512-bit bi-directional. Is this an accurate description? Does this mean the available read and write bandwidth is 4.8 GB/s each way as opposed to 9.6 GB/s bi-directional?
SL: The internal paths are actually much wider than 512-bit, but for each eDRAM module we have a 128-bit interface. This interface can be used for reading or writing the memory, so in total you have 9.6 GB/s of bandwidth. Based on the current load, this whole bandwidth can be used for reading or writing. In reality, the accesses to the memory are mixes of reads and writes.
Everybody has a bi-directional bus to the memory, nVIDIA, 3Dfx, Matrox and others have a 128-bit bi-directional bus, the XBA architecture has 512-bit bi-directional bus. Your question is probably based on Matrox's DualBus architecture - which means that they have separate read and write lines to the memory controller, after which the memory accesses are squeezed into the bi-directional 128-bit bus. So they have 256 data lines to the memory controller, XBA has more than 1000 data lines at this point.
|
|
|