Here is the official features list for the mobile Pentium III processor, taken directly from Intel's datasheets:
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Processor core/bus speeds
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featuring Intel SpeedStep technology
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Max Perf. Mode
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Batt. Optimized Mode
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1000/100 MHz @ 1.70V
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700/100 MHz @ 1.35V
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900/100 MHz @ 1.70V
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700/100 MHz @ 1.35V
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850/100 MHz @ 1.60V
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700/100 MHz @ 1.35V
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800/100 MHz @ 1.60V
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650/100 MHz @ 1.35V
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750/100 MHz @1.60V
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600/100 MHz @ 1.35V
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700/100 MHz @ 1.60V
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550/100 MHz @ 1.35V
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700/100 MHz @ 1.35V
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500/100 MHz @ 1.10V
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600/100 MHz @ 1.35V
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500/100 MHz @ 1.10V
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500/100 MHz @ 1.10V
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300/100 MHz @ 0.975V
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Supports the Intel Architecture with
Dynamic Execution
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On-die primary 16-Kbyte instruction cache
and 16-Kbyte write-back data cache
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On-die second level cache (256-Kbyte)
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Integrated GTL+ termination
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Integrated math co-processor
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Intel Processor Serial Number
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BGA2 and Micro-PGA2 packaging technologies
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Supports
thin form factor notebook designs
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Exposed
die enables more efficient heat dissipation
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Ultra
Low Voltage and Low Voltage mobile Intel Pentium III processors are only
available in BGA2 packages.
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Fully compatible with previous Intel
microprocessors
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Binary
compatible with all applications
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Support
for MMXTM technology
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Support
for Streaming SIMD Extensions
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Power Management Features
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Quick
Start and Deep Sleep modes provide low power dissipation
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On-die thermal diode
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Intel goes into further detail on the new features of the mobile Pentium III in their technical specification. That list is as follows:
Performance improved over existing mobile processors:
- Supports the Intel Architecture with Dynamic Execution
- Supports the Intel Architecture MMXTM technology
- Supports Streaming SIMD Extensions for enhanced video, sound, and 3D performance
- Supports Intel SpeedStep Technology
- Integrated Intel Floating Point Unit compatible with the IEEE 754 standard
On-die primary (L1) instruction and data caches:
- 4-way set associative, 32-byte line size, 1 line per sector
- 16-Kbyte instruction cache and 16-Kbyte write-back data cache
- Cacheable range controlled by processor programmable registers
On-die second level (L2) cache:
- 8-way set associative, 32-byte line size, 1 line per sector
- Operates at full core speed
- 256-Kbyte, ECC protected cache data array
GTL+ system bus interface:
- 64-bit data bus, 100-MHz operation
- Uniprocessor, two loads only (processor and I/O bridge/memory controller)
- Integrated termination
Pentium II processor clock control:
- Quick Start for low power, low exit latency clock "throttling"
- Deep Sleep mode for lower power dissipation
Thermal diode for measuring processor temperature