EPIC processors are capable of addressing a 64-bit memory space. In comparison, 32-bit x86 processors access a relatively small 32-bit address space, or up to 4GB of memory. The concept of a 64-bit memory space is immense and therefore difficult to get your mind around. At some point in the future, a 64-bit memory space may be a limiting factor to performance, but I believe that day is well off in the future. This gives the Itanium the memory addressing ability needed to meet current and foreseeable future high-end processing needs.
Through bank switching, x86 processors, such as the Intel Pentium III Xeon and the AMD Athlon, can address more than 4GB of memory. Unfortunately, there is hardware and software overhead to bank switching that harms performance and increases complexity.
The first generation of Itanium systems, using the 460GX chipset, will be expandable with up to 64GB of memory. Generations beyond that will be able to take more memory. Higher end Itanium systems designed by the likes of SGI, IBM and HP should eventually be able to take far more than 64GB. While it may be hard to imagine 4GB or even 64GB of memory being a bottleneck to performance, when you consider SGI has mentioned plans to eventually build machines using 512 Itanium processors accessing more than a terabyte of data in main memory, 64GB of memory, let alone 4GB, begins to look rather small.
When you have a massive amount of data to process you need to access and process in real-time, a RAID attached by FCAL may not cut it. The EPIC architecture and Itanium are intended in part for just such situations, where in order to get acceptable performance, a system needs more than 4GB, or 64GB, of main memory.