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Sharky Extreme :


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- AMD Unleashes Six-Core Desktop CPU
- WD Doubles Capacity of Fastest SATA Drive
- Nvidia Announces Blazing GeForce GTX 480, 470 GPUs
- SanDisk's SSD As Rapid As It Is Reliable
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Features

- PC Buyer's Guide for Gaming Enthusiasts -- January 2012
- PC Buyer's Guide for Entry-Level Gaming -- January 2012
- Build Your Own Gaming PC Guide -- Nov. 2011
- PC Buyer's Guide for Gaming Enthusiasts, August, 2011
- July Entry-Level Gaming PC Guide

Buyer's Guides

- PC Buyer's Guide for Entry-Level Gaming -- January 2012
- Build Your Own Gaming PC Guide -- Nov. 2011
- February High-end Gaming PC Buyer's Guide
- November Value Gaming PC Buyer's Guide
- September Extreme Gaming PC Buyer's Guide

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  • Humus asks: What are you going to do about the memory bandwidth problem? Radeon has its HyperZ technology, Kyro has deferred rendering, 3dfx was working on HSR, but what can we expect from Nvidia?

    NVIDIA: Our plan is to implement a combination of z-occlusion culling (not rendering occluded pixels) and a radically efficient memory controller (with access granularity to the pixel level) based on sophisticated crossbar architecture.

    applemaggot asks: A dual-channel DDR SDRAM memory architecture (like the one in the upcoming NVidia Crush motherboard chipset) provides double the memory bandwidth almost for free, what problems would be associated with implementing such a system on an NVidia 3D accelerator? To me this new feature seems like it would be the magic bullet in the fight against the memory bandwidth barrier. What are the chances that we'll see such a novel system added to NV20, or perhaps future NVidia 3D products?

    NVIDIA: A dual-channel DDR SDRAM implementation implies 2 64-bit channels. All high-end NVIDIA graphics processors already implement 128-bit DDR memory interfaces, and in fact, offer more memory bandwidth than any core-logic-based 128-bit DDR system as they can run at higher frequencies due to easier loading conditions. (Typically frame buffers are single loaded, while main memory systems use DIMMS and typically have many loads, reducing the frequency.)

    asadsalm asks: Is there any way you people can make a GeForce MX fit on a PCMCIA card? It might take up two PCMCIA cards space (either vertically or horizontally), and it might have less RAM to conserve space. And if it is possible, then do you have plans to manufacture it in the near future? This will solve the problem for many people who want 3D graphics on their notebook/laptop but can't because of their Video Card limitations.

    NVIDIA: The physical space is not the issue; a data path to draw to the laptop display is the issue. PCMCIA cards basically implement PCI, which delivers about 90MB/sec shared for the entire PCI Bus. (Peak transfer rate is 132MB/sec) PCMCIA cards do not have the ability to write to the laptop display directly, which means they would either need to copy the frame buffer data across PCI into the laptop's frame buffer – which would be very slow, or try to copy the data using zoom video, a low-bandwidth video port that exists on some laptops. Neither of these solutions would actually provide significant graphics acceleration to the integrated laptop display, as the bottleneck would be copying the frame buffer from the PCMCIA card “into” the laptop's frame buffer for display for every frame. It would be possible to design a PCMCIA graphics card that would drive an external display, at similar performance to PCI-based video card solutions, but to date no manufacturer has expressed interest in such a solution.

    jvadgaard asks: In terms of future technologies, what measures will be taken to improve on the fillrate bottleneck? Is dual-channel memory being considered?

    NVIDIA: Dual-channel implies a RAMBUS solution, or perhaps two 64-bit DDR interfaces. NVIDIA has chosen to implement 128-bit DDR frame buffer interfaces, which offers more than 2x the memory bandwidth of dual-channel RAMBUS memory subsystems. In addition to offering the highest memory bandwidth available, NVIDIA continues to push technologies that make ever more efficient use of memory bandwidth.





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