Since the main consideration for PC memory solutions is cost, DRAM has necessarily been designed with cheaper and slower components, while SRAM has been used sparingly as cache. In order to keep the costs down, there are relatively few variations of DRAM, which allows the manufacturers to make them in huge volumes. On the other hand, SRAM chips are generally custom designed for specific applications, such as external cache, fast communication switches, etc. By far the most common use for SRAM today is cache applications in PCs.

In order to improve the rate at which data can be output (other than simply speeding up the internal operations), a number of special features have been implemented in both SRAM and DRAM memories. These features have allowed some internal operations to be bypassed or hidden for transfers after the first access of a series of data requests. Many of the features were first implemented on SRAM chips, and only recently have been used on DRAMs. Before discussing these features, we will cover basic memory architecture and operations.

Memory operations are controlled by a variety of signals, each of which has its own 'signal pin'. The voltage on the appropriate pin is set either high or low, depending upon what operation is being performed. These signal pins allow the addresses to be selected, read or write operations to be determined and the data to be output, with the majority being for address selection and data output.