All DRAM memory designs have the same basic core, and thus the same internal speeds and relatively large latency periods. The different 'flavors' of DRAM can all be described as variations of the operation described here. On the other hand there are many different types of SRAM, many of which are proprietary designs. The SRAM operation described here is simply provided to give an understanding of how SRAM is different from DRAM. Note also that while this description is for an asynchronous interface, all cache SRAM used today are synchronous (see the discussion on asynchronous vs. synchronous interfaces which follows).

Here is the description of an asynchronous SRAM read and write, along with a simple block diagram for illustration.

SRAM Read

1) Row and column addresses are sent to the address pins, the Chip Select pin is set low (/CS) and Write Enable is set high (/WE)
2) The Output Enable pin is set low (/OE) to signal data is to be sent to the outputs (this can be signaled at any time prior to the actual read of the cell)
3) Data is sent to the output pins after a specified address access time has elapsed.

SRAM Write

1) The row and column addresses are sent to the address lines, /CS is set low, and /WE is set low.
2) The data is latched in from the input pins. (A latch is a simple register which holds data)
3) The data is stored in the selected cell.

For both of these operations, there is a setup time (the amount of time necessary to set and stabilize /CS, /WE and the address signals) and a hold time (the amount of time the signals must be held after the clock signal goes high). The access time of the SRAM is the amount of time it takes to read the data after all of the timing requirements have been met.