New memory solutions are attempting to address the bandwidth issue. D-RDRAM is the one Intel is banking on. One problem with increasing the bus speed is the 'ringing', or noise on the circuit. Rambus has addressed this with a 16-bit interface and a point-to-point protocol. While the maximum bandwidth is increased to as high as 1.6GB/sec, the initial latency is actually a bit worse than SDRAM. Turnaround latency, however, is better than current solutions. With a projected cost increase of up to 50% over current solutions, it is not very attractive at this point.
PC133 will increase the bandwidth from 800MB/sec to 1.06GB/sec, but will do nothing for initial latency or turnaround latency. DDR SDRAM will increase the maximum bandwidth even further, to as much as 2.1GB/sec, but the latency issue still limits the effective bandwidth.
Cached DRAM is currently the favorite method being pushed to address the latency issue. By adding a small amount of SRAM cache, the latency is reduced to an average of 3 or 4 bus clock cycles, and therefore improves the bandwidth usage. Ramtron has been offering ESDRAM for several years, however it has been somewhat expensive and has only seen use in some niche markets.
Most recently, NEC introduced Virtual Channel Memory, which is another form of cached DRAM. The good news is that it can be added to any existing DRAM design, such as PC133 or DDR SDRAM. The bad news is that Ramtron has filed suit for patent infringement. VIA Technology has included support for VCM in their most recent chipsets, making it the favorite in the race to succeed in the mass market barring any injunctions from the litigation.
Unfortunately, there isn't much good information available about what these BIOS settings do. The first thing to recognize is that the BIOS settings are, for the most part, setting values in the chipset for various memory and I/O operations. Some of these also override the SDRAM internal timings, such as CAS Latency, by altering the values stored in the module SPD chip. This means that the BIOS settings available will depend upon which chipset is present, and what the manufacturer has decided to allow the user to modify.
Most manufacturers will offer two different default settings - one for slow, but stable operation and another for fast but potentially unstable operation. Most manufacturers have a BIOS defaults option, which is generally the conservative setting. The faster setting may be called 'Setup Defaults' or 'Turbo Defaults'. Unless you know precisely what is being affected by each BIOS setting, it is best to use these defaults or you may actually decrease system performance.
It is generally accepted that a quality motherboard manufacturer will provide default BIOS settings that provide the best performance and stability for their own design. Of course, there really isn't any 'best' setting for all circumstances, or there wouldn't be any point to allowing the settings to be modified. In addition, each manufacturer may offer different options in their BIOS than others even when using the same chipset.
To illustrate this point, consider the following BIOS settings for the VIA VP3 and MVP3 chipsets from one manufacturer:
| BIOS Setting |
Chipset Register & Bits |
| Bank 0/1 DRAM Timing |
Dev 0, Reg 64, Bits 7-6-2 |
| Bank 2/3 DRAM Timing |
Dev 0, Reg 65, Bits7-6-2 |
| Bank 4/5 DRAM Timing |
Dev 0, Reg 66, Bits7-6-2 |
| SDRAM CAS Latency |
Dev 0, Reg 67, Bits5-4 |
| DRAM Read Pipeline |
Dev 0, Reg 53, Bit 4 |
| SRAM Bank Interleave |
Dev 0, Reg 65-64, Bit1-0 |
| Cache Rd+CPU Wt Pipeline |
Dev 0, Reg 53, Bit 6-5 |