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Sharky Extreme :




One of the most eagerly awaited technologies for 2000 is undoubtedly 3dfx' VSA-100 (voodoo scaleable architecture), which was announced at last month's Comdex. Although we've yet to see real silicon in action (just the Quantum 3D Mercury systems), the fill rates being mentioned for the Voodoo4/5 are very appealing.

Learning their lessons from SLI (scan line interleave) with the Voodoo2, 3dfx' is looking to go a few steps above and beyond SLI with Voodoo 5 cards, which will use multiple VSA-100 processors. The Voodoo 5 architecture is actually capable of running up to 32 processors in an SLI setup. Quantum3D will be making VSA-100 powered systems with 8-32 processors and up to 2GB of RAM in their AAlchemy product line. That comes to over 100 Gigapixels/second fill rate and $ 40,000. But the ultimate 3D gaming board will most likely be the Voodoo5 6000, with 128MB, 1.33-1.47 Gigapixels and four VSA-100 chips working in tandem (all for $600). But how does this technology work? We went straight to the source, Scott Sellers, co-founder and CTO at 3dfx, and asked him to explain exactly what the secret to this 'new' SLI is.

Scott Sellers:

"Ok, let's try this,

For the 2 chip configurations, there are various modes of operation:
Mode #1: SLI mode with no FSAA. In this mode, each chip, in parallel, renders scanline "bands". The particular band height is programmable, between 1 and 128 scanlines (power of 2). So, for example, one chip would render scanlines 1-32, while the next would render 33-64, etc. In this mode, then, each chip renders 2 pixels per clock, but since both are operating in parallel we achieve 4 pixels per clock throughput. Note that in this mode since we're not performing FSAA that each chip only renders one subsample per pixel (in other words, only pixels are rendered, not sub-pixels/sub-samples)

Mode #2: SLI mode with 2-sample anti-aliasing (FSAA): In this mode, each chip, in parallel, renders scanline "bands." However, we can set each chip up render 2 sub-samples per pixel. Therefore, since each chip is rendering 2 sub-samples per pixel, our effective fill-rate drops in half to 2 pixels per clock (each chip will render 1 pixel per clock since we're rendering 2 sub-samples, but since we have 2 chips running in parallel we achieve 2 pixels per clock sustained fillrate).





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