The original Celeron 300A-533 processors didn't have many of these original Pentium III Katmai limitations and were already ahead of the game with a full-speed, on-die L2 cache. As such, the transition from the .25 micron Celeron core to the .18 micron Coppermine core is a much smoother one for the Celeron line, and doesn't really represent the quantum shift that it was for the Pentium III. The L2 cache size of the new Celerons remain unchanged at 128K, compared to the Pentium III Coppermine's full 256K. A smaller die size will certainly have positive aspects, but any upgrade from previous Celeron CPUs will be made in the area of further cache improvements and additional Coppermine enhancements.
- 0.18 micron Process Technology
- System bus frequency at 66 MHz
- 1.5 volt core voltage
- 128 KB on-die, full speed Level 2 (L2) cache with Error Correcting Code (ECC)
- Dual Independent Bus (DIB) architecture: Separate dedicated external System Bus and dedicated internal high-speed cache bus
- Internet Streaming SIMD Extensions (SSE) for enhanced video, sound and 3D performance
- Binary compatible with applications running on previous members of the Intel microprocessor line
- Dynamic execution micro architecture
- Power Management capabilities
- -System Management mode
- -Multiple low-power states
- Optimized for 32-bit applications running on advanced 32-bit operating systems
- Flip Chip Pin Grid Array (FC-PGA) packaging technology; FC-PGA processors deliver high performance with improved handling protection and socketability
- Integrated high performance 16 KB instruction and 16 KB data, nonblocking, level one cache
- Double Quad Word Wide (256bit) cache data bus provides extremely high throughput on read/store operations.
- 8-way cache associativity provides improved cache hit rate on reads/store operations.
- Error-correcting code for System Bus data
|