The Celeron uses 128K of 8-way set-associative L2 cache. That's twice the L2 cache of the Duron, which will likely significantly impact performance. For this reason, AMD brings up the fact that the Duron's total on-chip cache, including L1 cache, is 192K, compared to the Celeron's lower 160K of on-die cache. The AMD Thunderbird uses 256K of L2 cache, giving it a total of 384K of on-die cache.

Another major feature of the Duron's cache architecture is that its L1 and L2 cache are exclusive, just like with the Thunderbird. According to AMD, it is not necessary for data to be duplicated in both L1 and L2 cache with the Duron's exclusive cache system like it is with the Intel Celeron's inclusive cache system. So, AMD says, this increases the usable on-die cache size of the Duron from 64K to 192K, while the Celeron only has 128K of usable on-die cache.

The Duron uses the same 100MHz double-pumped (so call it 200MHz) front side bus that the Athlon has used since day one. The speedy FSB gives the processor plenty of bandwidth to communicate with the chipset, removing the FSB as a major bottleneck. Like with the Athlon, memory speed will depend on the chipset in use, though AMD expects that most Duron systems will ship with PC100 memory for cost reasons.

The Duron's 200MHz FSB speed compares very favorably with the Celeron's 66MHz FSB speed. Three times the FSB bandwidth is nothing to sneeze at. The Celeron's memory speed is dependent on the chipset though, so both systems are on the same level in that aspect. While FSB speed impacts performance, it's the final performance that matters.