The Duron has a thoroughly modern CPU core design that leverages much of the AMD Thunderbird's technology. It sports 64K of L1 data cache, 64K of L1 instruction cache, three independent integer pipelines, three address calculation pipelines, and a fully pipelined, out-of-order, three-way floating-point engine. The actual silicon layout is different for the Duron and Thunderbird, but from an end user's perspective, the Duron and Athlon core are functionally identical.

The Celeron sports only 16K of L1 data and 16K of L1 instruction cache. Four times the L1 cache is nothing to sneeze at, and can lead to a massive performance boost. At the same time, the large amount of L1 cache may be partially responsible for the Duron's relatively high power usage.

The Duron sports 64K of full speed 16-way set-associative L2 cache. Essentially, the purpose of associativity is to reduce cache conflicts in hardware rather than software, where a programmer would have to address these conflicts, which is ideal but not practical. For unoptimized programs, set-associative caches increase the cache "hit" rate and can reduce execution time, especially in multithreaded applications. By adding various other features, such as redundant columns (ensures cache integrity), and more write back and fill buffers (reduces the chance of the processor waiting for data and stalling), AMD has ensured that the Athlon is well optimized for heavy bandwidth loads.

The Celeron uses 128K of 8-way set-associative L2 cache. That's twice the L2 cache of the Duron, which will likely significantly impact performance. For this reason, AMD brings up the fact that the Duron's total on-chip cache, including L1 cache, is 192K, compared to the Celeron's lower 160K of on-die cache. The AMD Thunderbird uses 256K of L2 cache, giving it a total of 384K of on-die cache.

Another major feature of the Duron's cache architecture is that its L1 and L2 cache are exclusive, just like with the Thunderbird. According to AMD, it is not necessary for data to be duplicated in both L1 and L2 cache with the Duron's exclusive cache system like it is with the Intel Celeron's inclusive cache system. AMD says this increases the usable on-die cache size of the Duron from 64K to 192K, while the Celeron only has the equivalent of 128K of usable on-die cache.

The Duron uses the same 100MHz double-pumped (so call it 200MHz) front side bus that the Athlon has used since day one. The speedy FSB gives the processor plenty of bandwidth to communicate with the chipset, removing the FSB as a major bottleneck. As with the Athlon, memory speed will depend on the chipset in use, though AMD expects that most Duron systems will ship with PC100 memory for cost reasons.

The Duron's 200MHz FSB speed compares very favorably with the Celeron's 66MHz FSB speed. Three times the FSB bandwidth is nothing to sneeze at. Our testing with Celerons running on a 66MHz FSB versus slower Celerons overclocked to near speeds with a faster FSB shows to our satisfaction that the 66MHz FSB is crippling the Celeron's performance, thereby giving the Duron a major speed advantage.