• 8-way set associative, 1024 sets
  
• 32 byte line (32 bytes data, 4 bytes ECC) every 2 clocks, equals 11.7GB/sec throughput at 733MHz
  
• 36-bit physical address space
  
• 4 x reduction in latency versus Katmai P3 L2
  
• Cache bus speed fully scalable with core frequency
  
• 288-bit transfer width (256 data, 32 ECC)
  
• 2 cycle back to back throughput
  

• 6 Fill Buffers (increased from 4) offer increase of 50% in concurrent non-blocking data cache operations.
  
• 8 Bus Queue Entries (increased from 4) allow more outstanding memory/bus operations.
  
• 4 Writeback Buffers (increased from 1) offer reduced blocking during cache replacement operations along with faster deallocation time for fill buffers.
  

• Decrease in minimum gate dimension for improved transistor speed.
  
• Fluorine-doped SiO2 (SiOF) dielectric for reduced capacitance resulting in global speed increase.
  

• Additional metal layer for routing density enables full-speed integrated L2 interface.
  

As the specs show, the Coppermine core offers a host of smaller improvements, along with the packaging of the L2 cache on-die and faster front side bus speed (133MHz) support.

These additions will make themselves felt more early next year when recompiled SSE optimization routines are introduced to existing and new software via DirectX7, Intel's own Fortran95 Compiler 4.5, and Intel's C/C++ Compiler 4.5.