While AMD's Drew Prairie explained it thusly:
"KX133 and KT133 are feature-set equivalent from a user perspective, they both support AMD Athlon platform with AGP4x, 200Mhz FSB and PC133 --- one is designed for Slot A and the other for Socket A. There is no performance difference between the same frequency processor in Slot A versus Socket A. Socket A uses different electrical signaling than Slot A to pass signals
between the processor and the chipset. This (and the form factor of Socket vs. Slot) is the primary difference between Slot A and Socket A, so also the major difference between KX133 and KT133."
For those new to the game, however, we'll recap AMD's scheme to eliminate congestion on the system bus.
Clocked at 200MHz, the EV6 bus AMD licensed from DEC is the fastest implementation of an FSB available on the x86 market. Functioning somewhat like a backbone for the architecture, the EV6's magic lies in scalability - up to 400MHz for a peak bandwidth of 3.2GB/s! Although no plans have been made for such an implementation, AMD has promised 266MHz bus speeds by the end of the year. Currently transferring at 1.6GB/s, the EV6 can still theoretically push more information than Intel's 1.06GB/s at 133MHz.
Bandwidth Explained Slide
Asynchronous bus speeds such as the 200MHz system bus can be used thanks to source synchronous clocking (as opposed to Intel's GTL+ bus, which operates synchronously).
Imagine, if you will, a new Jaguar XKR (yes, the one with 370bhp) owner with a learner's permit. When driving around under the supervision of his Driving Instructor, he isn't allowed to drive faster than the speed limit. Whether it is through the "memory bus," the "AGP bus," or the "system bus," he is limited to a single speed (currently the 133MHz bus). On the other hand, while under the close eye of his "responsible" buddy, he has the freedom to floor it where appropriate and save a little time on his trip.
Using this source synchronous design, AMD has allowed the system bus extra speed without having to change, say, the memory bus where the "speed limit" is current memory technology. Of course, the above story is completely hypothetical, but demonstrates how AMD's architecture affords the option of increasing the speed in one location while keeping the others at a safe, standard level (surely driving everywhere at 100mph would earn a citation in no time).