VIA is supporting DDR in a big way. All of their future desktop chipsets that we know of will support DDR SDRAM. The upcoming and already shipping chipsets support DDR200 and 266. The next step will be DDR333, which we expect will ship in the second half of 2002. DDR333 on a 64-bit bus should have almost 2.7GBps of peak theoretical memory bandwidth, as compared to 2.1GBps for DDR266 memory.

The current and soon to ship chipsets also support PC133 SDR SDRAM memory. Since the acceptance and availability of DDR SDRAM was never certain, VIA built SDR SDRAM support in partially as a safety precaution. It also acts as a good transition chipset since VIA's design allows the building of boards that support both SDR and DDR SDRAM.

Currently, DDR prices are a bit higher than SDR prices, but all parties we've spoken to expect the price delta to shrink to nothing by the end of the year. Our only question is, with memory prices as low as they are today, might the price of SDR rise to the price of DDR instead of the price of DDR falling? We shudder to think.

VIA has a Pentium 4 DDR chipset in the works called the PX266. It will likely ship in Q3 of 2001 and should use V-Link, a technology we will cover later on. It will sport 64-bit PCI on the southbridge and support dual-processors.

At the recent Platform Conference, AMD displayed an early version of a Tyan motherboard bearing room for two Socket A processors. Yes, it was a board with AMD's 760MP chipset. At this time, VIA does not have an equivalent chipset in the works. AMD is rolling out their 760MP in a very limited fashion, starting with only Tyan, sometime in mid-2001. VIA is going to wait for AMD to prove themselves before committing to a MP Athlon chipset.

Unlike the MP Pentium chipsets VIA makes, making an AMD MP chipset is a bit more difficult. The EV6 bus is much quicker than Intel's P6 bus, but it is also point-to-point, meaning AMD's bus can only connect two components, the processor and the northbridge, not two processors and the northbridge like Intel's shared bus can. So in order to make an MP Athlon chipset, AMD had to put two EV6 busses. This increases the chipset die size and pin count, which thereby increases the chipset's cost. AMD has a shared bus architecture relying on LDT planned for their K8 series processors.

We frankly expect AMD to meet with some success with their MP chipset. Still, we're not sure whether they will meet with enough success to convince VIA to develop their own solution. Only time will tell.